library ieee;
use ieee.std_logic_1164.all;

-- This arbitrary state machine is probably not very useful in reality, but demonstrates 

entity fwd_test_2to1_mux11 is
    port (d0,d1               : in  std_logic_vector(10 downto 0);
          q                   : out std_logic_vector(10 downto 0);
          sel                 : in  std_logic
    );
end fwd_test_2to1_mux11;

architecture behavior of fwd_test_2to1_mux11 is

begin

process(sel,d0,d1)
	begin
	case sel is
		when '0' =>
		    q <= d0;
		when '1' => 
			q <= d1;
	end case;
end process;

end behavior;